One of the goals in the fabrication of electronic components is to minimize the size of various components. For example, it is desirable that hand held devices such as cellular telephones and personal digital assistants (PDAs) be as small as possible. To achieve this goal, the semiconductor circuits that are included within the devices generally should be as small as possible. One way of making these circuits smaller is to stack the chips that carry the circuits.
A number of ways of interconnecting the chips within the stack are known. For example, bond pads formed at the surface of each chip can be wire-bonded, either to a common substrate or to other chips in the stack. Another example is a so-called micro-bump 3D package, where each chip includes a number of micro-bumps that are routed to a circuit board, e.g., along an outer edge of the chip.
Yet another way of interconnecting chips within the stack is to use through-vias. Through-vias extend through the substrate thereby electrically interconnecting circuits on various chips stacked together. Through-via interconnections can provide advantages in terms of interconnect density compared to other technologies. However, introduction of such interconnects may introduce additional challenges.
The integration of chips in 3D brings forth new challenges that should be addressed. One of the challenges arises due to deleterious effects that through substrate vias may produce on active devices. One such effect arises due to the strain that may result from the formation of the through substrate vias. The strain from these through substrate vias may cause significant variation as well as systematic degradation of devices within the active circuitry. This problem is amplified as the number of through substrate vias is increased to increase integration of the stacked chips. Hence, what is needed in the art are improved structures and methods of producing through substrate vias without significantly impacting devices or components fabricated on the chips.